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rf pll frequency synthesizers data sheet adf4110/adf4111/adf4112/adf4113 rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures adf4110: 550 mhz ; adf4111: 1.2 ghz ; adf4112: 3.0 ghz ; adf4113: 4.0 ghz 2.7 v to 5.5 v p ower s upply separate c harge p ump s upply (v p ) a llows e xtended t uning v oltage in 3 v s ystems programmable d ual - m odulus p rescaler 8/9, 16/17, 32/33, 64/65 progra mmable c harge p ump c urrents programmable a ntibacklash p ulse width 3 - w ire s erial i nterface analog and d igital l ock d etect hardware and s oftware p ower - d own m ode a pplications base s tations for w ireless r adio (gsm, pcs, dcs, cdma, wcdma) wireless h andsets (g sm, pcs, dcs, cdma, wcdma) wireless lans communications t est e quipment c at v e quipment g eneral d escription t he adf4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and downcon - version sections of wireless receivers and transmitters. they consist of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters, and a dual - modulus prescaler (p/p + 1). the a (6 - bit) and b (13 - bit) c ounters, in conjunction with the dual - modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14 - bit reference counter (r counter) allows selectable refin frequencies at the pfd input. a complete phase - locked loop (pll) can be im plemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). control of all the on - chip registers is via a simple 3 - wire interface. the devices operate with a power supply ranging from 2.7 v to 5.5 v and can be powered down when not in use. f unctional b lock d iagram n = bp + a function latch prescaler p/p +1 13-bit b counter 6-bit a counter 14-bit r counter 24-bit input register r counter latch a, b counter latch phase frequency detector av dd sd out 19 13 14 22 sd out from function latch dgnd agnd ce rf in a rf in b le data clk ref in cpgnd v p dv dd av dd lock detect adf4110/adf4111 adf4112/adf4113 6 load load reference charge pump m3 m2 m1 high z mux muxout cp r set current setting 2 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 1 03496-0-001 figure 1 . functional block diagram
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 transistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 circuit description ......................................................................... 12 reference input section ............................................................. 12 rf input stage ............................................................................. 12 prescaler (p/p + 1) ...................................................................... 12 a and b counters ....................................................................... 12 r counter .................................................................................... 12 phase frequency detector (pfd) and char ge pump ............ 13 muxout and lock detect ........................................................... 13 input shift register .................................................................... 13 fun ction latch ............................................................................ 19 initialization latch ..................................................................... 20 device programming after initial power - up ......................... 20 resynchronizing the prescaler output .................................... 21 applications ..................................................................................... 22 local oscillator for gsm base station transmitter .............. 22 using a d/a converter to drive the r set pin ......................... 23 shutdown circuit ....................................................................... 23 wideband pll ............................................................................ 23 direct conversion modulator .................................................. 25 interfacing ................................................................................... 26 pcb design guidelines for chip scale package .................... 26 outline dimensions ....................................................................... 27 ordering guide ............................................................................... 28 r ev ision h istory 1 /1 3 rev. e to rev. f changes to table 1 ............................................................................. 4 changes to ordering guide ........................................................... 28 8 /12 rev. d to rev. e changed cp - 20- 1 to cp - 20- 6 ........................................... universal updated outline dimensions ........................................................ 28 changes to ordering guide ........................................................... 28 5/12 rev. c to rev. d changes to figure 2 ........................................................................... 5 change s to figure 4 and table 4 ...................................................... 7 updated outline dimensions ........................................................ 28 changes to ordering guide ........................................................... 28 3 /0 4 data s heet changed from r ev . b to r ev . c. updated format .................................................................. universal changes to specifications ................................................................. 2 changes to figure 32 ....................................................................... 22 changes to the ordering guide ..................................................... 28 3/03 data s h eet changed from r ev . a to r ev . b. edits to specifications ....................................................................... 2 updated outline dimensions ............................................. 24 1/01 data s heet changed from r ev . 0 to r ev . a. changes to dc specifications in b version, b chips, unit , and test conditions/comments c olumns ..................... 2 changes to abso lute maximum rating ......................................... 4 changes to fr in a function test ..................................................... 5 changes to figure 8 ........................................................................... 7 new graph added tpc 22 ........................................................... 9 change to pd polarity box in table v ......................................... 15 change to pd polarity box in table vi ........................................ 16 change to pd polarity paragraph ................................................. 17 addition of new material (pcb des ign guidelines for chip C scale package) ................ 23 replacement of cp - 20 outline with cp - 20 [2] outline ............ 24
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 3 of 28 s pecifications av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k ? ; dbm referred to 50 ? ; t a = t min to t max , unless otherwise noted . operating temperature range is as follows: b version: ? 40 c to +85 c. table 1 . parameter b version b chips 1 u nit test conditions/comments rf characteristics (3 v) see figure 29 for input circuit. rf input sensitivity ? 15/0 ? 15/0 dbm min/max rf input frequency adf4110 80/550 80/550 mhz min/max for lower frequencies, ens ure slew rate (sr) > 30 v/s. adf4110 50/550 50/550 mhz min/max input level = ? 10 dbm. adf4111 0.08/1.2 0.08/1.2 ghz min/max for lower frequencies, ensure sr > 30 v/s. adf4112 0.2/3.0 0.2/3.0 ghz min/max for lower frequencies, ensure sr > 75 v/s. adf4112 0.1/3.0 0.1/3.0 ghz min/max input level = ? 10 dbm . adf4113 0.2/3.7 0.2/3.7 ghz min/max input level = ? 10 dbm. for lower frequencies, ensure sr > 130 v/s. maximum allowable prescaler output frequency 2 165 165 mhz max rf characteristics (5 v ) rf input sensitivity ? 10/0 ? 10/0 dbm min/max rf input frequency adf4110 80/550 80/550 mhz min/max for lower frequencies, ensure sr > 5 0 v/s. adf4111 0.08/1.4 0.08/1.4 ghz min/max for lower frequencies, ensure sr > 5 0 v/s. adf4112 0. 1/3.0 0.1/3.0 ghz min/max for lower frequencies, ensure sr > 75 v/s. adf4113 0.2/3.7 0.2/3.7 ghz min/max for lower frequencies, ensure sr > 130 v/s. adf4113 0.2/4.0 0.2/4.0 ghz min/max input level = ? 5 dbm . maximum allowable prescaler output frequen cy 2 200 200 mhz max refin characteristics refin input frequency 5/104 5/104 mhz min/max for f < 5 mhz, ensure sr > 100 v/s. reference input sensitivity 0.4/av dd 0.4/av dd v p - p min/max av dd = 3.3 v, biased at av dd /2 . see note 3 . 3.0/av dd 3.0/av dd v p - p min/max av dd = 5 v, biased at av dd /2. see note 3 . refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector frequency 4 55 55 mhz max charge pum p i cp sink/source programmable (see table 9 ). high value 5 5 ma typ with r set = 4.7 k ? . low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 4.7 k ? . r set range 2.7/10 2.7/10 k ? typ see table 9 . i cp 3 - state leakage current 1 1 na typ sink and source current matching 2 2 % typ 0.5 v v cp v p C 0.5 v. i cp vs. v cp 1.5 1.5 % typ 0.5 v v cp v p C 0.5 v. i cp vs. temperature 2 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage dv dd C 0.4 dv dd C 0.4 v min i oh = 500 a. v ol , output low voltage 0.4 0.4 v max i ol = 500 a.
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 4 of 28 parameter b version b chips 1 u nit test conditions/comments power supplies av dd 2.7/5.5 2.7/5.5 v min/v max dv dd av dd av dd v p av dd /6.0 av dd /6.0 v min/v max av dd v p 6.0 v. see figure 25 and figure 26 . i dd 5 (ai dd + di dd ) adf4110 5.5 4.5 ma max 4.5 ma typical . adf4111 5.5 4.5 ma max 4.5 ma typical . adf4112 7.5 6.5 ma max 6.5 ma typical . adf 4113 11 8.5 ma max 8.5 ma typical . i p 0.5 0.5 ma max t a = 25c . low power sleep mode 1 1 a typ noise characteristics adf4113 normalized phase noise floor 6 ? 215 ?215 dbc/hz typ phase noise performance 7 @ vco output . adf4110: 540 mhz output 8 ? 91 ? 91 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4111: 900 mhz output 9 ? 87 ? 87 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4112: 900 mhz output 9 ? 90 ? 90 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4113: 900 mhz output 9 ? 91 ? 91 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4111: 836 mhz output 10 ? 78 ? 78 dbc/hz typ @ 300 hz offset and 30 khz pfd frequency . adf4112: 1 750 mhz output 11 ? 86 ? 86 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4112: 1750 mhz output 12 ? 66 ? 66 dbc/hz typ @ 200 hz offset and 10 khz pfd frequency . adf4112: 1960 mhz output 13 ? 84 ? 84 dbc/hz typ @ 1 khz offset and 200 khz pfd frequ ency . adf4113: 1960 mhz output 13 ? 85 ? 85 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency . adf4113: 3100 mhz output 14 ? 86 ? 86 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency . spurious signals adf4110: 540 mh z output 9 ? 97/ ? 106 ? 97/ ? 106 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4111: 900 mhz output 9 ? 98/ ? 110 ? 98/ ? 110 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4112: 900 mhz output 9 ? 91/ ? 100 ? 91/ ? 100 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4113: 900 mhz output 9 ? 100/ ? 110 ? 100/ ? 110 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . a df4111: 836 mhz output 10 ? 81/ ? 84 ? 81/ ? 84 dbc typ @ 30 khz/60 khz and 30 khz pfd frequency . adf4112: 1750 mhz output 11 ? 88/ ? 90 ? 88/ ? 90 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4112: 1750 mhz output 12 ? 65/ ? 73 ? 65/ ? 73 dbc typ @ 10 khz/20 khz and 10 khz pfd frequency . adf4112: 1960 mhz output 13 ? 80/ ? 84 ? 80/ ? 84 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4113: 1960 mhz output 13 ? 80/ ? 84 ? 80/ ? 84 dbc typ @ 200 khz/400 khz and 200 khz pfd frequency . adf4113: 3100 mhz output 14 ? 80/ ? 82 ? 82/ ? 82 dbc typ @ 1 mhz/2 mhz and 1 mhz pfd frequency . 1 the b c hip specifications are given as typical value s. 2 this is the maximum operating frequency of th e cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 3 ac coupling ensures av dd /2 bias. see figure 33 for a typical circuit. 4 guaranteed by d esign. 5 t a = 25 c; av dd = dv dd = 3 v; p = 16; sync = 0; dly = 0; rf in for adf4110 = 540 mhz; rf in for adf4111, adf4112, adf4113 = 900 mhz. 6 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the output of the vco , pn to t , and subtracting 20logn (where n is the n divider value) and 10logf pfd : pn synth = pn tot C 10logf pfd C 20logn. 7 the phase noise is measured with the ev - adf411xsd1z e valuation b oard and the hp8562e s pectrum a nalyzer. the spectrum analyzer provides the ref in for the synthesizer (f refout = 10 m hz @ 0 dbm). sync = 0; dly = 0 ( table 7 ). 8 f refin = 10 mhz; f pfd = 200 khz; o ffset frequency = 1 khz; f rf = 540 mh z; n = 2700; loop b/w = 20 khz. 9 f refin = 10 mhz; f pfd = 200 khz; o ffset freq uency = 1 khz; f rf = 900 mhz; n = 4500; l oop b/w = 20 khz. 10 f refin = 10 mhz; f pfd = 30 khz; o ffset frequency = 300 hz; f rf = 836 mhz; n = 27867; l oop b/w = 3 khz. 11 f refin = 10 mhz; f pfd = 200 khz; o ffset frequency = 1 khz; f rf = 1750 mhz; n = 8750; l oop b/w = 20 khz 12 f refin = 10 mhz; f pfd = 10 khz; o ffset frequency = 200 hz; f rf = 1750 mhz; n = 175000; l oop b/w = 1 khz. 13 f refin = 10 mhz; f pfd = 200 khz; o ffset frequency = 1 khz; f rf = 1960 mhz; n = 9800; l oop b/w = 20 khz. 14 f refin = 10 mhz; f pfd = 1 mh z; o ffset frequency = 1 khz; f rf = 3100 mhz; n = 3100; l oop b/w = 20 khz.
data sheet adf4110/adf4111/adf4112/adf4113 rev. f | page 5 of 28 timing characteristics guaranteed by design but not production tested. av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6 v; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k; t a = t min to t max , unless otherwise noted. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulse width cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 4 t 5 t 6 03496-002 figure 2. timing diagram
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 6 of 28 a bsolute m aximum r atings t a = 25c, unless otherwise noted table 3 . parameter rating av dd to gnd 1 ? 0.3 v to +7 v av dd to dv dd ? 0.3 v to +0.3 v v p to gnd ? 0.3 v to +7 v v p to av dd ? 0.3 v to +5.5 v digital i/o voltage to gnd ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd ? 0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd ? 0.3 v to v dd + 0.3 v rf in a to rf in b 320 mv operating temperature range industrial (b version) ? 40c to +85c storage temperature range ? 65c to +150c maximum junction temperature 150c tssop ja thermal impedance 150.4c/w lfcsp ja thermal impedance (paddle soldered) 122c /w lfcsp ja thermal impedance (paddle not soldered) 216c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv , and it is esd sensitive. proper precautions should be taken for handling and assembly. t ransistor c ount 6425 (cmos) and 303 (bipolar). esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 7 of 28 pin configurations a nd function descript ions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dv dd muxout le v p data clk ce dgnd r set cp cpgnd agnd rf in b rf in a av dd ref in top view (not to scale) adf4110 adf4111 adf4112 adf4113 03496-0-003 03496-0-004 notes 1. the exposed paddle should be connected to agnd. 14 1 3 12 1 3 4 le 15 muxout data clk 11 ce cpgnd agnd 2 agnd rf in b 5 rf in a 7 av dd 6 av dd 8 ref in 9 dgnd 10 dgnd 19 r set 20 cp 18 v p 17 dv dd 16 dv dd adf4110 adf4111 adf4112 adf4113 top view (not to scale) figure 3 . tssop pin configuration figure 4 . lfcsp pin configuration table 4 . pin function d escriptions tssop pin no. lfcsp pin no. mnemonic function 1 19 r set connecting a resistor bet ween this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.56 v. the relationship between i cp and r set is set max cp r i = so, with r set = 4.7 k ? , i cpmax = 5 ma . 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 4 2, 3 agnd anal og ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 29. 6 5 rf in a input to the rf prescaler. this small - signal input is ac - coupled from the vco. 7 6, 7 av dd analog power supply. this may range from 2.7 v to 5.5 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 , and an equivalent input resistance of 100 k ? . see figure 28 . this input can be driven from a ttl or cmos crystal oscillator, or can be ac - coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three - state mode. taking the pin high powers up the device dep ending on the status of the power - down bit f2. 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift register on the clk rising edge. this input is a high impedan ce cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in the shift r egisters is loaded into one of the four latches; the latch is selected using the control bits. 14 15 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd digital power supply. this may range from 2.7 v to 5.5 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump power supply. this should be gre ater than or equal to v dd . in systems where v dd is 3 v, v p can be set to 6 v and used to drive a vco with a tuning range of up to 6 v. 1 epad exposed pad (lfcsp only). the exposed paddle should be connected to agnd.
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 8 of 28 typical performance characteristic s freq param data keyword impedance ? unit ? type ? format ? ohms ghz s ma r 50 freq mags11 angs11 1.05 0.9512 ? 40.134 1.10 0.93458 ? 43.747 1.15 0.94782 ? 44.393 1.20 0.96875 ? 46.937 1.25 0.92216 ? 49.6 1.30 0.93755 ? 51.884 1.35 0.96178 ? 51.21 1.40 0.94354 ? 53.55 1.45 0.95189 ? 56.786 1.50 0.97647 ? 58.781 1.55 0.98619 ? 60.545 1.60 0.95459 ? 61.43 1.65 0.97945 ? 61.241 1.70 0.98864 ? 64.051 1.75 0.97399 ? 66.19 1.80 0.97216 ? 63.775 freq mags11 angs11 0.05 0.89207 ? 2.0571 0.10 0.8886 ? 4.4427 0.15 0.89022 ? 6.3212 0.20 0.96323 ? 2.1393 0.25 0.90566 ? 12.13 0.30 0.90307 ? 13.52 0.35 0.89318 ? 15.746 0.40 0.89806 ? 18.056 0.45 0.89565 ? 19.693 0.50 0.88538 ? 22.246 0.55 0.89699 ? 24.336 0.60 0.89927 ? 25.948 0.65 0.87797 ? 28.457 0.70 0.90765 ? 29.735 0.75 0.88526 ? 31.879 0.80 0.81267 ? 32.681 0.85 0.90357 ? 31.522 0.90 0.92954 ? 34.222 0.95 0.92087 ? 36.961 1.00 0.93788 ? 39.343 03496-0-005 figure 5. s - parameter data for the adf4113 rf input (up to 1.8 ghz) ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 rf input power (dbm) 0 1 2 3 4 5 rf input frequency (ghz) 03496-0-006 v dd = 3v v p = 3v t a = +85 c t a = +25 c t a = ? 40 c figure 6 . input sensitivity (adf4113) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 2.0khz ? 1.0khz 900mhz 1.0khz 2.0khz frequency 03496-0-007 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 s averages = 19 reference level = ? 4.2dbm ? 91.0dbc/hz figure 7. adf4113 phase noise (900 mhz, 200 khz, 20 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 2.0khz ? 1.0khz 900mhz 1.0khz 2.0khz frequency 03496-0-008 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 s averages = 19 reference level = ? 4.2dbm ? 92.5dbc/hz figure 8 . adf4113 phase noise (900 mhz, 200khz, 20 khz) with dly and sync enabled ? 140 ? 130 ? 120 ? 1 1 0 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 phase noise (dbc/hz) frequency offset from 900mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-009 rms noise = 0.52 r l = ? 40dbc/hz figure 9 . adf4113 integrated phase noise (900 mhz, 200 khz, 20 khz, typical lock time: 400 s) ? 140 ? 130 ? 120 ? 1 1 0 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 phase noise (dbc/hz) frequency offset from 900mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-010 rms noise = 0.62 r l = ? 40dbc/hz figure 10 . adf4113 integrated phase noise (900 mhz, 200 khz, 35 khz, typical lock time: 200 s)
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 9 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 output power (db) ?400khz ?200khz 900mhz 200khz 400khz frequency 03496-0-0 1 1 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5s averages = 30 reference level = ?4.2dbm ?90.2dbc/hz figure 11 . adf4113 reference spurs (900 mhz, 200 khz, 20 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 400khz ? 200khz 900mhz 200khz 400khz frequency 03496-0-012 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5s averages = 30 reference level = ? 4.2dbm ? 89.3dbc/hz figure 12 . adf4113 (900 mhz, 200 k hz, 35 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 400hz ? 200hz 1750mhz 200hz 400hz frequency 03496-0-013 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 10 reference level = ? 8.0dbm ? 75.2dbc/hz figure 13 . adf4113 phase noise (1750 mhz, 30 khz, 3 khz) ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 phase noise (dbc/hz) frequency offset from 1750mhz carrier (hz) 1k 100 10k 100k 1m 03496-0-014 rms noise = 1.6 r l = ?40dbc/hz figure 14 . adf4113 integrated phase noise (1750 mhz, 30 khz, 3 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 80khz ? 40khz 1750mhz 40khz 80khz frequency 03496-0-015 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 3hz video bandwidth = 3hz sweep = 255s positive peek detect mode reference level = ? 5.7dbm ? 79.6dbc/hz figure 15 . adf4113 reference s purs (1750 mhz, 30 khz, 3 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 2.0khz ? 1.0khz 3100mhz 1.0khz 2.0khz frequency 03496-0-016 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9s averages = 45 reference level = ? 4.2dbm ? 86.6dbc/hz figure 16 . adf4113 phase noise (3100 mhz, 1 mhz, 100 khz)
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 10 of 28 ? 140 ? 130 ? 120 ? 1 1 0 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 phase noise (dbc/hz) frequency offset from 3100mhz carrier (hz) 10 3 10 2 10 4 10 5 10 6 03496-0-017 rms noise = 1.7 r l = 40dbc/hz figure 17 . adf4113 integrated phase noise (3100 mhz, 1 mhz, 100 khz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 output power (db) ? 2.0mhz ? 1.0mhz 3100mhz 1.0mhz 2.0mhz frequency 03496-0-018 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 13s averages = 1 reference level = ? 17.2dbm ? 80.6dbc/hz figure 18 . reference spurs (3100 mhz, 1 mhz, 100 khz) ?180 ?170 ?160 ?150 ?140 ?130 ?120 phase noise (dbc/hz) phase detect or frequency (khz) 10 1 100 1000 10000 03496-0-019 v dd = 3v v p = 5v figure 19 . adf4113 phase noise (referred to cp output) vs. phase detector frequency phase noise (dbc/hz) ? 100 ? 90 ? 80 ? 70 ? 60 ? 40 ? 20 0 20 40 60 80 100 temper a ture ( c ) 03496-0-020 v dd = 3v v p = 3v figure 20 . adf4113 phase noise vs. temperature (900 mhz, 200 khz, 20 khz) first reference spur (dbc) ?100 ?90 ?80 ?70 ?60 ?40 ?20 0 20 40 60 80 100 tempera ture (c) 03496-0-021 v dd = 3v v p = 5v figure 21 . adf4113 reference spurs vs. temperature (900 mhz, 200 khz, 20 khz) ? 105 ? 95 ? 85 ? 75 ? 65 ? 55 ? 45 ? 35 ? 25 ? 15 ? 5 first reference spur (dbc) 0 1 2 3 4 5 tuning vo lt age (v ) 03496-0-022 v dd = 3v v p = 5v figure 22 . adf4113 reference spurs (200 khz) vs. v tune (900 mhz, 200 khz, 20 khz)
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 11 of 28 phase noise (dbc/hz) ?100 ?90 ?80 ?70 ?60 ?40 ?20 0 20 40 60 80 100 tempera ture (c) 03496-0-023 v dd = 3v v p = 5v figure 23 . adf4113 phase noise vs. temperature (836 mhz, 30 khz, 3 khz) first reference spur (dbc) ? 100 ? 90 ? 80 ? 70 ? 60 ? 40 ? 20 0 20 40 60 80 100 temper a ture ( c ) 03496-0-024 v dd = 3v v p = 5v figure 24 . adf4113 reference spurs vs. temperature (836 mhz, 30 khz, 3 khz) 0 1 2 3 4 5 6 7 8 9 10 ai dd (ma) prescaler v alue 8/9 0 16/17 32/33 64/65 03496-0-025 adf4113 adf4112 adf4110 adf4111 figure 25 . ai dd vs. prescaler value 0 0.5 1.0 1.5 2.0 2.5 3.0 di dd (ma) prescaler output frequency (mhz) 50 0 100 150 200 03496-0-026 v dd = 3v v p = 3v figure 26 . di dd vs. prescaler output frequency (adf4110, adf4111, adf4112, adf4113) ? 6 ? 4 ? 2 ? 3 ? 5 0 ? 1 i cp (ma) 2 1 4 3 6 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v cp (v) 03496-0-027 v pp = 5v i cp = 5ma figure 27 . charge pump output characteristics for adf4110 family
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 12 of 28 circuit description reference input section the reference input stage is shown in figure 28. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 03496-0-028 figure 28. reference input stage rf input stage the rf input stage is shown in figure 29. it is followed by a two-stage limiting amplifier to generate the current mode logic (cml) clock levels needed for the prescaler. av dd agnd 500 ? 500 ? 1.6v bias generator rf in a rf in b 03496-0-029 figure 29. rf input stage prescaler (p/p + 1) along with the a and b counters, the dual-modulus prescaler (p/p + 1) enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a and b counters. the prescaler is programmable; it can be set in software to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. a and b counters the a and b cmos counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 200 mhz or less. thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r . the equation for the vco frequency is f vco = [( p b ) + a ] f refin / r where: f vco = output frequency of external voltage controlled oscillator (vco) p = preset modulus of dual-modulus prescaler b = preset divide ratio of binary 13-bit counter(3 to 8191) a = preset divide ratio of binary 6-bit swallow counter (0 to 63) f refin = output frequency of the external reference frequency oscillator r = preset divide ratio of binary 14-bit programmable reference counter (1 to 16383) r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. 13-bit b counter 6-bit a counter prescaler p/p + 1 from rf input stage modulus control n = bp + a load load to pfd 03496-0-030 figure 30. a and b counters
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 13 of 28 p hase f requency d etector (pfd) and c harge p ump the pfd takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. fig ure 31 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. tw o bits in the reference counter latch, abp2 and abp1, control the width of the pulse. see table 7 . p programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider cp output r divider n divider cp cpgnd v 03496-0-031 figure 31 . pfd simplified schematic and timing (in lock) muxout and lock dete ct the output multiplexer on the adf4110 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. table 9 shows the full truth table. figure 32 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock d etect is set high when the phase error on three consecutive phase detector (pd) cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it stays high until a phase error greater than 25 ns is detected on any subsequent pd cycle. the n - channel open - drain analog lock detect should be operated with a 10 k ? nominal external pull - up resistor. when lock has been detected, this output is high with narrow low - going pulses. control mux dv dd muxout dgnd analog lock detect digital lock detect r counter output n counter output sdout 03496-0-032 figure 32 . muxout circuit input shift register the adf4110 family digital section includes a 24 - bit input shift register, a 14 - bit r counter, and a 19 - bit n counter comprised of a 6 - bit a counter and a 13 - bit b counter. data is clocked into the 24 - b it shift register on each rising edge of clk msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. th ese are the two lsbs, db1 and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . table 6 shows a summary of how the latches are programmed. table 5 . c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch (including prescaler) 1 1 initialization latch
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 14 of 28 table 6 . ad f4110 family latch summary n counter latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 b13 b12 b11 b8 b7 b6 b5 b4 b2 b1 a6 a5 a4 a3 a2 a1 c2 (0) c1 (1) b3 13-bit b counter control bits reserved db2 db1 db0 g1 b10 b9 6-bit a counter n i a g p c function latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (0) f5 timer counter control control bits prescaler value db2 db1 db0 pd2 cpi3 cpi2 - r e w o p 2 n w o d muxout control current setting 1 current setting 2 k c o l t s a f e d o m k c o l t s a f e l b a n e p c - e e r h t e t a t s d p y t i r a l o p - r e w o p 1 n w o d r e t n u o c t e s e r p1 p2 initialization latch db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) f5 timer counter control control bits prescaler value db2 db1 db0 pd2 cpi3 cpi2 - r e w o p 2 n w o d muxout control current setting 1 current setting 2 k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p - r e w o p 1 n w o d r e t n u o c t e s e r p1 p2 test mode bits db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 ldp t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter, r control bits d e v r e s e r db2 db1 db0 sync dly abp2 abp1 anti- backlash width sync dly k c o l t c e t e d n o i s i c e r p reference counter latch x x x x = don't care x = don't care 03496-0-033
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 15 of 28 table 7 . reference counter latch map operation ldp three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 0 1 test mode bits should be set to 00 for normal operation r14 0 0 0 0 ? ? ? 1 1 1 1 r13 0 0 0 0 ? ? ? 1 1 1 1 r12 0 0 0 0 ? ? ? 1 1 1 1 r3 0 0 0 1 ? ? ? 1 1 1 1 r2 0 1 1 0 ? ? ? 0 0 1 1 r1 1 0 1 0 ? ? ? 0 1 0 1 divide ratio 1 2 3 4 ? ? ? 16380 16381 16382 16383 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? test mode bits db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 ldp t2 t1 r14 r13 r12 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 c2 (0) c1 (0) r9 14-bit reference counter control bits d e v r e s e r db2 db1 db0 sync dly abp2 abp1 anti- backlash width sync dly k c o l t c e t e d n o i s i c e r p abp1 abp2 0 0 1 1 0 1 0 1 3.0ns 1.5ns 6.0ns 3.0ns antibacklash pulse width sync dly 0 0 1 1 0 1 0 1 normal operation output of prescaler is resynchronized with nondelayed version of rf input normal operation output of prescaler is resynchronized with delayed version of rf input operation x x = don't care 03496-0-034
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 16 of 28 table 8 . ab counter latch map these bits are not used by the device and are don't care bits a6 0 0 0 0 ? ? ? 1 1 1 1 a5 0 0 0 0 ? ? ? 1 1 1 1 a2 0 0 1 1 ? ? ? 0 0 1 1 a1 0 1 0 1 ? ? ? 0 1 0 1 a counter divide ratio 0 1 2 3 ? ? ? 60 61 62 63 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b13 0 0 0 0 0 ? ? ? 1 1 1 1 b12 0 0 0 0 0 ? ? ? 1 1 1 1 b11 0 0 0 0 0 ? ? ? 1 1 1 1 b3 b2 b1 b counter divide ratio ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 1 ? ? ? 1 1 1 1 0 0 1 1 0 ? ? ? 0 0 1 1 0 1 0 1 0 ? ? ? 0 1 0 1 not allowed not allowed not allowed 3 4 ? ? ? 8188 8189 8190 8191 13-bit b counter db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 b13 b12 b11 b8 b7 b6 b5 b4 b2 b1 a6 a5 a4 a3 a2 a1 b3 6-bit a counter reserved db2 g1 b10 b9 n i a g p c *see table 9 f4 (function latch) fastlock enable* cp gain operation 0 0 1 1 0 1 0 1 charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent upon which fastlock mode is used. see function latch description. n = bp + a, p is prescaler value set in the function latch, b must be greater than or equal to a. for continuously adjacent values of (n x f ref ), at the output, n min is (p 2 ? p). x x = don't care x c2 (0) c1 (1) control bits db1 db0 03496-0-035
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 17 of 28 table 9 . function latch map m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output analog lock detect (n-channel open-drain) serial data output dgnd f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 phase detector polarity negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f5 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 p1 0 1 0 1 prescaler value 8/9 16/17 32/33 64/65 p2 0 0 1 1 cpi6 cpi3 cpi5 cpi2 cpi4 cpi1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 2.7k ? 4.7k ? 10k ? 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 current setting 2 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2(1) c1(0) f5 control bits prescaler value db2 db1 db0 pd2 p1 cpi3 cpi2 - r e w o p 2 n w o d current setting 1 timer counter control k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p muxout control - r e w o p 1 n w o d r e t n u o c t e s e r p2 tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 see function latch, timer counter control section 03496-0-036
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 18 of 28 table 10 . initializa tion latch map m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 output three-state output digital lock detect (active high) n divider output dv dd r divider output analog lock detect (n-channel open-drain) serial data output dgnd tc4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tc3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 tc2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 tc1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 timeout (pfd cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 f1 0 1 counter operation normal r, a, b counters held in reset f2 0 1 phase detector polarity negative positive f3 0 1 charge pump output normal three-state 0 1 1 1 ce pin pd2 pd1 mode asynchronous power-down normal operation asynchronous power-down synchronous power-down x x 0 1 x 0 1 1 f5 x 0 1 fastlock mode fastlock disabled fastlock mode 1 fastlock mode 2 f4 0 1 1 p1 0 1 0 1 prescaler value 8/9 16/17 32/33 64/65 p2 0 0 1 1 cpi6 cpi3 cpi5 cpi2 cpi4 cpi1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 2.7k ? 4.7k ? 10k ? 1.09 2.18 3.27 4.35 5.44 6.53 7.62 8.70 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 0.29 0.59 0.88 1.76 1.47 1.76 2.06 2.35 current setting 2 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db13 cpi6 cpi5 cpi4 cpi1 tc4 tc3 tc2 tc1 f4 f3 f2 m3 m2 m1 pd1 f1 c2 (1) c1 (1) f5 control bits prescaler value db2 db1 db0 pd2 p1 cpi3 cpi2 - r e w o p 2 n w o d current setting 1 timer counter control k c o l t s a f e d o m k c o l t s a f e l b a n e p c e t a t s - e e r h t d p y t i r a l o p muxout control - r e w o p 1 n w o d r e t n u o c t e s e r p2 see function latch, timer counter control section 03496-0-037
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 19 of 28 f unction l atc h the on - chip function latch is programmed w ith c2, c1 set to 1. table 9 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when db2 is 1, the r counter and the ab counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit must be disabled, and the n counter resumes counting in close alignment with the r counter. (the maximum error is one prescaler cycle.) power - down db3 (pd1) and db21 (pd2) on the adf411 x provide program - mable power - down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asynchronous powe r - down, the device powers down immediately after latching a 1 into b it pd1, provided pd2 has been loaded with a 0. in the programmed synchronous power - down, the device power - down is gated by the charge pump to prevent unwanted frequency jumps. once power - d own is enabled by writing a 1 into b it pd1 ( provided a 1 has also been loaded to pd2), the device goes into power - down on the next charge pump event. when a power - down is activated (either synchronous or asynchronous mode including ce pin activated power - d own), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three - state mode. ? the digital clock detect circuitry is reset. ? the rfin inpu t is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on - chip multiplexer is controlled by m3, m2, and m1 on the adf4110 family. table 9 shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. fastlock is enables o nly when this is 1. fastlock mode bit db10 of the function latch is the fastlock enable bit. when fastlock is enabled, this bit determines whic h fastlock mode is used. if the fastlock mode bit is 0, fastlock mode 1 is selected ; if the fastlock mode bit is 1, f astlock m ode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. th e device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 the charge pump current is switched to the contents of cu rrent setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 through tc1, the cp gain bit in the ab counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see table 9 for the timeout periods. timer counter control the user has the option of programming two charge pump c ur - rents. current setting 1 is meant to be used when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). the normal sequence of events is as follows: the user initially decides what the preferred charge pump currents are going to be. for example, they may choose 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. this is controlled by the timer counter control bits , db14 through db11 (tc4 through tc1) in the function latch. the truth table is given in table 10 . a user can program a new output frequency simply by pro - gramming the ab counter latch with new values for a and b. at the same time, the cp gain bit can be set to 1, which sets the charge pump with the value in cpi6 C cpi4 for a period deter - mined by tc4 through tc 1. when this time is up, the charge pump current reverts to the value set by cpi3 C cpi1. at the same time, the cp gain bit in the ab counter latch is reset to 0 and is ready for the next time the user wishes to change the frequency.
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 20 of 28 note that there is an e nable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cp i4 program current setting 2 for the charge pump. the truth table is given in table 10 . prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less tha n or equal to 200 mhz. thus, with an rf frequency of 2 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not. pd polarity this bit sets the phase detector polarity bit. see table 10 . cp three - state this bit controls the cp output pin. with the bit set high, the cp output is put into three - state. with the bit set low, the cp output is enabled. initialization latch when c2, c1 = 1, 1, the initialization latch is programmed. this is essentially the same as the function latch (programmed when c2, c 1 = 1, 0). however, when the initialization latch is programmed, an addi - tional internal reset pulse is applied to the r and ab counters. this pulse ensures that the ab counter is at load point when the ab counter data is latched , and the device begi n s cou nting in close phase alignment. if the latch is programmed for synchronous power - down (ce pin high; pd1 bit high; pd2 bit low), the internal pulse also triggers this power - down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. when the first ab counter data is latched after initialization, the internal reset pulse is again activated. however, successive ab counter loads after this will not trigg er the internal reset pulse. device programming a fter initial power - up after initial power - up of the device, there are three ways to program the device. initialization latch method apply v dd . program the initialization latch (11 in 2 lsbs of input word). m ake sure the f1 bit is programmed to 0. then , do an r load (00 in 2 lsbs). then do an ab load (01 in 2 lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, a, b, and timeout counters to load state conditions and three - states the charge pump. note that the prescaler band gap reference and the oscil - lator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3 . latching the first ab counter data after the initialization word activate s the same internal reset pulse. successive ab loads do not trigger the internal reset pulse unless there is another initialization. ce pin method 1. apply v dd . 2. bring ce low to put the device into power - down. this is an asynchronous power - down in that it happens immediately. 3. program the function latch (10). program the r counter latch (00). program the ab counter latch (01). 4. bring ce high to take the device out of power - down. the r and ab counters now resume counting in close alignment. a fter ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buf fer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method 1. apply v dd . 2. do a function lat ch load (10 in 2 lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. do an r counter load (00 in 2 lsbs). do an ab counter load (01 in 2 lsbs). do a function latch load (10 in 2 lsbs). as part of this, load 0 to the f1 bit. this d isables the counter reset. this sequence provides the same close alignment as the initiali - za tion method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three states the charge pump but does n ot trigger synchronous power - down. the counter reset method requires an extra function latch load compared to the initialization latch method.
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 21 of 28 resynchronizing the prescaler outpu t table 7 (the reference counter latch map) shows two bits, db22 and db21, which are labeled dly and sync, respectively. these bits affect the operation of the prescaler. with sync = 1, the prescaler output is resynchronized with the rf input. this has the effect of reducing jitter due to the prescaler a nd can lead to an overall improvement in synthesizer phase noise performance. typically, a 1 db to 2 db improvement is seen in the adf4113. the lower bandwidth devices can show an even greater improvement. for example, the adf4110 phase noise is typically improved by 3 db when sync is enabled. with dly = 1, the prescaler output is resynchronized with a delayed version of the rf input. if the sync feature is used on the synthesizer, some care must be taken. at some point, (at certain temperatures and output frequencies), the delay through the prescaler coincide s with the active edge on rf input ; this cause s the sync feature to break down. i t is important to be aware of this when using the sync feature. adding a delay to the rf signal, by programming dly = 1 , extend s the operating frequency and temperature somewhat. using the sync feature also increase s the value of the ai dd for the device. with a 900 mhz output, the adf4113 ai dd increases by about 1.3 ma when sync is enabled and by an additional 0.3 ma if dl y is enabled. all the typical performance plots i n this data sheet , except for figure 8 , apply for dly and sync = 0, i.e., no resynchroniza - tion or delay enabled.
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 22 of 28 applications local oscillator for gsm base station tra n s mitter figure 33 shows the adf4111/adf4112/adf4113 being used with a vco to produce the lo for a gsm base station transmitter. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? . a typical gsm system would have a 13 mhz tcxo driving the reference input with - out any 50 ? t ermination. in order to have channel spacing of 200 khz (gsm standard), the reference input must be divided by 65, using the on - chip reference divider of the ad f4111/ adf4112/adf4113. the charge pump output of the adf4111/adf4112/adf4113 (pin 2) drives the loop filter. in calculating the loop filter component values, a number of items need to be considered. in this example, the loop filter was designed so that th e overall phase margin for the system would be 45 degrees. othe r pll system specifications are k d = 5 ma k v = 12 mhz/v loop bandwidth = 20 khz f ref = 200 khz n = 4500 extra reference spur attenuation = 10 db all of these specifications are needed and used to come up with the loop filter component values shown in figure 33. the loop filter output drives the vco, which in turn is fed back to the rf input of the pll synthesizer. it also drives the rf out - put terminal. a t - circuit conf iguration provides 50 ? matching between the vco output, the rf output, and the rf in terminal of the synthesizer. in a pll system, it is important to know when the system is in lock. in figure 33 , this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be pro - grammed to monitor various internal signals in the synthesizer. one of these is the ld or lock - detect signal. adf4111 adf4112 adf4113 ce clk data le 1000pf 1000pf ref in 100pf cp muxout cpgnd agnd dgnd 1nf 8.2nf 620pf 100pf 51 ? 1 3.3k ? 5.6k ? 100pf 18 ? 1 to be used when generator source impedance is 50 ? . 2 optional matching resistor depending on rf out frequency. decoupling capacitors on av dd , dv dd , and v p of the adf411x and on the positive supply of the vco190-902t have been omitted from the diagram to increase clarity. spi compatible serial bus r set rf in a rf in b av dd dv dd v p fref in v dd v p lock detect v cc vco190-902t 18 ? 18 ? 100pf rf out 4.7k ? 7 15 16 8 2 14 6 5 1 9 4 3 b c p 51 ? 2 03496-0-038 figure 33 . local oscillator for gsm b ase station
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 23 of 28 adf4111 adf4112 adf4113 2.7k ? vco gnd 18 ? 100pf 100pf 18 ? 18 ? rf out fref in 51 ? 100pf 100pf rf in a rf in b power supply connections and decoupling capacitors are omitted for clarity. r set ref in cp loop filter ce clk data le spi compatible serial bus ad5320 12-bit v-out dac muxout lock detect input output 2 14 6 5 1 8 03496-0-039 figure 34 . driving the r set pin with a d/a converter using a d/a converter t o drive t he r set pin a d/a converter can be used to drive the r set pin of the adf4110 family , thus increas ing the level of control over the charge pump current , i cp . this can be a dvantageous in wide - band applications where the sensitivity of the vco varies over the tuning range. to compensate for this, the i cp may be varied to maintain good phase margin and ensure loop stability. see figure 34. shutdown cir cuit the attached circuit in figure 35 shows how to shut down both the adf4110 family and the accompanying vco. the adg701 switch goes closed circuit when a logic 1 is applied to the in input. the low cost switch is available in bo th sot - 23 and msop packages. wideband pll many of the wireless applications for synthesizers and vcos in plls are narrow band in nature. these applications include the various wireless standards like gsm, dsc1800, cdma, and wcdma. in each of these cases, t he total tuning range for the local oscillator is less than 100 mhz. however, there are also wideband applications for which the local oscillator could have a tuning range as wide as an octave. for example, cable tv tuners have a total range of about 400 m hz. figure 36 shows an application where the adf4113 is used to control and program the micronetics m3500 - 2235. the loop filter was designed for an rf output of 2900 mhz, a loop bandwidth of 40 khz, a pfd frequency of 1 mhz, i cp of 10 ma (2.5 ma synthesizer i cp multiplied by the gain factor of 4), vco k d of 90 mhz/v (sensitivity of the m3500 - 2235 at an output of 2900 mhz), and a phase margin of 45 c. in narrow - band applications, there is generally a small variation in output frequen cy (generally less than 10%) and a small variation in vco sensitivity over the range (typically 10% to 15%). however, in wideband applications , both of these parameters have a much greater variation. in figure 36 , for example, ther e is a ? 25% and +17% variation in the rf output from the nominal 2.9 ghz. the sensitivity of the vco can vary from 120 mhz/v at 2750 mhz to 75 mhz/v at 3400 mhz (+33%, ? 17%). variations in these parameters change the loop bandwidth. this in turn can affect stabil ity and lock time. by changing the programmable i cp , it is possible to get compensa - tion for these varying loop conditions and ensure that the loop is always operating close to optimal conditions.
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 24 of 28 v dd v p av dd dv dd adf4110 adf4111 adf4112 adf4113 v p 4.7k ? vco v cc gnd 18 ? 18 ? 18 ? 100pf 100pf rf out ref in 51 ? 100pf 100pf d n g p c d n g a d n g d rf in a rf in b decoupling capacitors and interface signals have been omitted from the diagram to increase clarity. r set cp ce power-down control v dd s in d gnd loop filter adg701 fref in 1 8 7 15 16 2 6 5 9 4 3 10 03496-0-040 figure 35 . local oscillator sh utdown circuit v dd v p av dd dv dd adf4113 v p 2.8nf 680? 130pf 3.3k? 19nf m3500-2235 v cc 18? 18? 18? 100pf 100pf rf out 1000pf 1000pf 51? ref in muxout lock detect 51? 100pf 100pf d n g p c d n g a d n g d rf in a rf in b ce clk data le s u b l a i r e s e l b i t a p m o c - i p s decoupling capacitors on av dd , dv dd , v p of the adf4113 and on vcc of the m3500-2250 have been omitted from the diagram to aid clarity. r set cp 4.7k? 12v v_tune gnd 20v 1k? ad820 3k? out fref in 3 4 9 5 6 14 2 1 8 7 15 16 03496-0-041 figure 36 . wideband phase - locked loop
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 25 of 28 direct conversion mo dulator in some applications , a direct conversion architecture can be used in base station transmitters. figure 37 shows the combina - tion available from adi to implement this solution. the circuit diagram shows the ad9761 being used with the ad8346. the use of dual integrated dacs such as the ad9761 with specified 0.02 db and 0.004 db gain and offset matching characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator (lo) is implemented using the adf4113. in this case, the osc 3b1 - 13m0 provides the stable 13 mhz reference frequency. the system is designed f or a 200 khz channel spacing and an output center frequency of 1960 mhz. the target application is a wcdma base station transmitter. typical phase noise performance from this lo is ? 85 dbc/hz at a 1 khz offset. the lo port of the ad8346 is driven in single - ended fashion. loin is ac - coupled to ground with the 100 pf capacitor ; loip is driven through the ac coupling capacitor from a 50 ? source. an lo drive level of between ? 6 dbm and ? 12 dbm is required. the circuit of figure 37 give s a typical level of ? 8 dbm. the rf output is designed to drive a 50 ? l oad but must be ac - coupled as shown in figure 37 . if the i and q inputs are driven in quadrature by 2 v p - p signals, the resulting output power is around ? 10 d bm. r set adf4113 18 ? 100pf 18 ? ref in 100pf rf in a rf in b cp serial digital interface tcxo osc 3b1-13m0 100pf 620pf 3.9k ? 3.3k ? 9.1nf 4.7k ? 18 ? 100pf rf out power supply connections and decoupling capacitors are omitted from diagram to increase clarity. ad9761 txdac refio fs adj modulated digital data qoutb iouta ioutb qouta ad8346 loin loip vout 100pf 100pf 2k ? 51 ? 910pf vco190-1960t ibbp ibbn qbbp qbbn low-pass filter low-pass filter 03496-0-042 figure 37 . direct conversion t ransmitter solution
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 26 of 28 interfacing the adf4110 family has a simple spi ? compatible serial inter - face for writing to the device. sclk, sdata, and le control the data transfer. when latch enable (le) goes high, the 24 bits that have been clocked into the input register on each rising edge of sclk get transferred to the appropriate latch. see figure 2 for the t iming d iagram and table 5 for th e l atch t ruth t able. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz , or one update every 1.2 s. this is certainly more than adequate for systems that have typical lock times in the hundreds of microseconds. aduc812 interface figure 38 shows the interface between the adf4110 family and the aduc812 m icro c onverter ? . since the aduc812 is based on an 8051 core, this interface can be used with any 8051 based m icrocontroller. the microconverter is set up for spi m aster m ode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4110 family needs a 24 - bit word. this is accomplished by writing three 8 - bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. when power is first applied to the adf4110 family, three writes are needed (one each to the r counter latch, n counter lat ch, and initialization latch) for the output to become active. i/o port lines on the aduc812 are also used to control power - down (ce input) , and to detect lock (muxout configured as lock detect and polled by the port input). when the aduc812 is operating i n the mode described above, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. sclock mosi i/o ports aduc812 sclk sdata le ce muxout (lock detect) adf4110 adf4111 adf4112 adf4113 03496-0-043 figure 38 . aduc812 to adf4110 family interface adsp - 2181 in terface figure 39 shows the interface between the adf4110 family and the adsp - 21xx digital signal processor. the adf4110 family needs a 24 - bit serial word for each latch write. the easiest way to accomplish this using the adsp - 21xx family is to use the auto buffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. sclk dt i/o flags adsp-21xx sclk sdata le ce muxout (lock detect) adf4110 adf4111 adf4112 adf4113 tfs 03496-0-044 figure 39 . adsp - 21xx to adf4110 family interface set up the word length for 8 bits and use three memory locations for each 24 - bit word. to program each 24 - bit latch, store the three 8 - bit bytes, enable the auto buffered mode, and then write to the transmit register of the dsp. this last opera - tion initiates the autobuffer transfer. p cb design guidelines f or chip scale package the lands on the chip scale package (cp - 20) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wide r than the package land width. the land should be centered on the pad. this ensure s that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensure s that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm , and the via barrel should be plated with 1 oz. co pper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
data sheet adf4110 /adf4111/adf4112/adf4113 rev. f | page 27 of 28 o utline d imensions 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant t o jedec standards mo-220-wggd-1. b o t t o m v i e w t o p v i e w e x p o s e d p a d p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indica t or 2.30 2.10 sq 2.00 for prope r connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 2 0 6 1 0 1 1 1 5 1 6 5 08-16-2010-b figure 40 . 20 - lead lead frame chip scale package [lfcsp _ w q ] 4 mm 4 mm body, very very thin quad (cp - 20 - 6) dimens ions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 41 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters
adf4110/adf4111/adf4112/adf4113 data sheet rev. f | page 28 of 28 ordering guide model 1 temperature range package description package option 2 adf4110bcpz C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4110bcpz -rl C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4110bcpz - rl7 C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4110bru C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4110bru - reel C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4110bru - reel7 - 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4110bruz C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4110bruz - rl C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4110bruz - rl7 C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4111bcpz C 4 0c to +85c 20 - lead frame chip scale package [lfcsp_ w q] cp - 20 - 6 adf4111bcpz -rl C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4111bcpz - rl7 C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4111bru C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4111bruz C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4111bruz - rl C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4111bruz - rl7 C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4112bcpz C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4112bcpz -rl C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4112bcpz - rl7 C 4 0c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4112bru C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4112bru - reel7 C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4112bruz C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4112bruz - reel C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4112bruz - reel7 C 40c to +85c 16 - lead thin shrink small outline package [tssop] ru - 16 adf4113bcpz C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf4113bcpz - rl C 40c to +85c 20 - lead frame chip scale package [lfcsp_ w q] cp - 20 - 6 adf4113bcpz - rl7 C 40c to +85c 20- lead frame chip scale package [lfcsp_ w q] cp -20-6 adf41 13bru C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4113bru - reel7 C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4113bruz C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4113bruz - r eel C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4113bruz - reel7 C 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adf4113bchips C 40c to +85c die eval - adf4113ebz1 evaluation board eval - adf4113ebz2 evaluation board ev - adf411xsd1z evaluation board 1 z = rohs compliant part. 2 cp - 20- 6 package was formerly cp - 20- 1 package. purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the p hilips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03496 - 0 - 1/13(f)

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